module ISAXes(	
  	input       	clk_i,
                	rst,
	input	[31:0]	RdInstr_w_i,
  	input	[31:0]	RdRS1_mplus1_i,
  	input	[31:0]	RdRS2_mplus1_i,
  	input 			RdIValid_ISAX1_mplus1_i,
  	output	[31:0]	WrRd_mplus1_o,
  	output        	WrRd_mplus1_valid_o
);
reg [31:0] RdIValid_ISAX1_mplus1_i_old;
reg [2:0]  counter; 

always @(posedge clk_i) begin 
	if(rst) 
		RdIValid_ISAX1_mplus1_i_old <= 0; 
	else 
		RdIValid_ISAX1_mplus1_i_old <= RdIValid_ISAX1_mplus1_i;
end

always @(posedge clk_i) begin 
	if(rst) 
		counter <= 0; 
	else if((RdIValid_ISAX1_mplus1_i && (RdIValid_ISAX1_mplus1_i_old != RdIValid_ISAX1_mplus1_i)) | ( counter<3 && RdInstr_w_i[14:12]==3'b010)) 
		counter <= counter +1;
end

assign WrRd_mplus1_o = RdRS2_mplus1_i + RdRS1_mplus1_i + 5; 
assign WrRd_mplus1_valid_o = RdIValid_ISAX1_mplus1_i & (~counter[0]);

endmodule


module testbench();


endmodule


module top( 
	input         		clk_i,
    input         		rst_i,
	input               debug_bus_cmd_valid,
	output reg          debug_bus_cmd_ready,
	input               debug_bus_cmd_payload_wr,
	input      [7:0]    debug_bus_cmd_payload_address,
	input      [31:0]   debug_bus_cmd_payload_data,
	output reg [31:0]   debug_bus_rsp_data,
	output              debug_resetOut,
	input               timerInterrupt,
	input               externalInterrupt,
	input               softwareInterrupt,
	output     [31:0]   iBusAhbLite3_HADDR,
	output              iBusAhbLite3_HWRITE,
	output     [2:0]    iBusAhbLite3_HSIZE,
	output     [2:0]    iBusAhbLite3_HBURST,
	output     [3:0]    iBusAhbLite3_HPROT,
	output     [1:0]    iBusAhbLite3_HTRANS,
	output              iBusAhbLite3_HMASTLOCK,
	output     [31:0]   iBusAhbLite3_HWDATA,
	input      [31:0]   iBusAhbLite3_HRDATA,
	input               iBusAhbLite3_HREADY,
	input               iBusAhbLite3_HRESP,
	output     [31:0]   dBusAhbLite3_HADDR,
	output              dBusAhbLite3_HWRITE,
	output     [2:0]    dBusAhbLite3_HSIZE,
	output     [2:0]    dBusAhbLite3_HBURST,
	output     [3:0]    dBusAhbLite3_HPROT,
	output reg [1:0]    dBusAhbLite3_HTRANS,
	output              dBusAhbLite3_HMASTLOCK,
	output     [31:0]   dBusAhbLite3_HWDATA,
	input      [31:0]   dBusAhbLite3_HRDATA,
	input               dBusAhbLite3_HREADY,
	input               dBusAhbLite3_HRESP, 
	input				debugReset, 
	output [31:0] res_3_val
);

	wire  	[31:0] 	RdInstr_w_i;
  	wire  	[31:0]	RdRS1_mplus1_i;
  	wire	[31:0]	RdRS2_mplus1_i;
  	wire 			RdIValid_ISAX1_mplus1_i;
  	wire 	[31:0]	WrRd_mplus1_o;
  	wire       		WrRd_mplus1_valid_o;

	wire	[32 -1 : 0]	WrRD_3_o;
    wire				WrRD_validReq_3_o;
    wire	[32 -1 : 0] RdInstr_2_i;
    wire	[32 -1 : 0] RdRS1_2_i;
    wire	[32 -1 : 0] RdRS2_2_i;
    wire				RdFlush_2_i;
    wire				RdFlush_3_i;
    wire 	[32 -1 : 0] RdInstr_3_i;

ISAXes ISAXes_inst(
	clk_i,
	rst_i,
	RdInstr_w_i,
	RdRS1_mplus1_i,
	RdRS2_mplus1_i,
	RdIValid_ISAX1_mplus1_i,
	WrRd_mplus1_o,
	WrRd_mplus1_valid_o
);

SCAL SCAL_inst(   
	.clk_i(clk_i),
    .rst_i(rst_i),
	//	Interface to the ISAXes
	.WrRD_ISAX1_3_i(WrRd_mplus1_o),
	.WrRD_validReq_ISAX1_3_i(WrRd_mplus1_valid_o),
	.RdInstr_2_o(RdInstr_w_i),
	.RdRS1_2_o(RdRS1_mplus1_i),
	.RdRS2_2_o(RdRS2_mplus1_i),
	.RdIValid_ISAX1_2_o(RdIValid_ISAX1_mplus1_i),
	//	Interface to the Core
	.WrRD_3_o(WrRD_3_o),
	.WrRD_validReq_3_o(WrRD_validReq_3_o),
	.RdInstr_2_i(RdInstr_2_i),
	.RdRS1_2_i(RdRS1_2_i),
	.RdRS2_2_i(RdRS2_2_i),
	.RdFlush_2_i(RdFlush_2_i),
	.RdFlush_3_i(RdFlush_3_i),
	.RdInstr_3_i(RdInstr_3_i)
);

VexRiscv VexRiscv_inst(
	.debug_bus_cmd_valid(debug_bus_cmd_valid),
	.debug_bus_cmd_ready(debug_bus_cmd_ready),
	.debug_bus_cmd_payload_wr(debug_bus_cmd_payload_wr),
	.debug_bus_cmd_payload_address(debug_bus_cmd_payload_address),
	.debug_bus_cmd_payload_data(debug_bus_cmd_payload_data),
	.debug_bus_rsp_data(debug_bus_rsp_data),
	.debug_resetOut(debug_resetOut),
	.timerInterrupt(timerInterrupt),
	.externalInterrupt(externalInterrupt),
	.softwareInterrupt(softwareInterrupt),
	
	.WrRD_3_i(WrRD_3_o),
	.WrRD_validReq_3_i(WrRD_validReq_3_o),
	.RdInstr_2_o(RdInstr_2_i),
	.RdRS1_2_o(RdRS1_2_i),
	.RdRS2_2_o(RdRS2_2_i),
	.RdFlush_2_o(RdFlush_2_i),
	.RdFlush_3_o(RdFlush_3_i),
	.RdInstr_3_o(RdInstr_3_i),

  
	.iBusAhbLite3_HADDR        (iBusAhbLite3_HADDR     ),
	.iBusAhbLite3_HWRITE       (iBusAhbLite3_HWRITE    ),
	.iBusAhbLite3_HSIZE        (iBusAhbLite3_HSIZE     ),
	.iBusAhbLite3_HBURST       (iBusAhbLite3_HBURST    ),
	.iBusAhbLite3_HPROT        (iBusAhbLite3_HPROT     ),
	.iBusAhbLite3_HTRANS       (iBusAhbLite3_HTRANS    ),
	.iBusAhbLite3_HMASTLOCK    (iBusAhbLite3_HMASTLOCK ),
	.iBusAhbLite3_HWDATA       (iBusAhbLite3_HWDATA    ),
	.iBusAhbLite3_HRDATA       (iBusAhbLite3_HRDATA    ),
	.iBusAhbLite3_HREADY       (iBusAhbLite3_HREADY    ),
	.iBusAhbLite3_HRESP        (iBusAhbLite3_HRESP     ),
	.dBusAhbLite3_HADDR        (dBusAhbLite3_HADDR     ),
	.dBusAhbLite3_HWRITE       (dBusAhbLite3_HWRITE    ),
	.dBusAhbLite3_HSIZE        (dBusAhbLite3_HSIZE     ),
	.dBusAhbLite3_HBURST       (dBusAhbLite3_HBURST    ),
	.dBusAhbLite3_HPROT        (dBusAhbLite3_HPROT     ),
	.dBusAhbLite3_HTRANS       (dBusAhbLite3_HTRANS    ),
	.dBusAhbLite3_HMASTLOCK    (dBusAhbLite3_HMASTLOCK ),
	.dBusAhbLite3_HWDATA       (dBusAhbLite3_HWDATA    ),
	.dBusAhbLite3_HRDATA       (dBusAhbLite3_HRDATA    ),
	.dBusAhbLite3_HREADY       (dBusAhbLite3_HREADY    ),
	.dBusAhbLite3_HRESP        (dBusAhbLite3_HRESP     ),
	.clk                       (clk_i                  ),
	.reset                     (rst_i                  ),
	.debugReset                (debugReset                  )
);	

endmodule